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dc.contributor.authorReaz, MBI
dc.contributor.authorAmin, Nowshad
dc.contributor.authorIbrahimy, MI
dc.contributor.authorMohd-Yasin, F
dc.contributor.authorMohammad, A
dc.date.accessioned2017-05-03T11:49:40Z
dc.date.available2017-05-03T11:49:40Z
dc.date.issued2008
dc.date.modified2012-09-04T22:55:42Z
dc.identifier.isbn978-1-4244-1642-4
dc.identifier.issn0840-7789
dc.identifier.doi10.1109/CCECE.2008.4564488
dc.identifier.urihttp://hdl.handle.net/10072/40072
dc.description.abstractA zero skew clock routing methodology has been developed to help design team speed up their clock tree generation process. The methodology works by breaking up the clock net into smaller partitions, then inserting clock buffers to drive each portion, and lastly, routing the connection from original clock source to each newly inserted clock buffers with zero skew. A few Perl scripts and a new Visual Basic based routing tool have been developed to support the methodology implementation. The routing algorithm used in this tool is based on the exact zero skew routing algorithm. The methodology has been tested using a real design database and resulting in a significant improvement in the through put time required to complete the clock tree generation. This improvement is attributed to the ability to generate clock tree on much smaller portions of clock nets that supports of speeding up the clock tree generation process in IC design.
dc.description.peerreviewedYes
dc.description.publicationstatusYes
dc.format.extent123535 bytes
dc.format.mimetypeapplication/pdf
dc.languageEnglish
dc.language.isoeng
dc.publisherIEEE
dc.publisher.placeUnisted STates
dc.relation.ispartofstudentpublicationN
dc.relation.ispartofconferencenameCanadian Conference on Electrical and Computer Engineering
dc.relation.ispartofconferencetitle2008 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-4
dc.relation.ispartofdatefrom2008-05-04
dc.relation.ispartofdateto2008-05-07
dc.relation.ispartoflocationNiagara Falls, CANADA
dc.relation.ispartofpagefrom23
dc.relation.ispartofpageto+
dc.rights.retentionY
dc.subject.fieldofresearchElectrical and Electronic Engineering not elsewhere classified
dc.subject.fieldofresearchcode090699
dc.titleZero skew clock routing for fast clock tree generation
dc.typeConference output
dc.type.descriptionE1 - Conferences
dc.type.codeE - Conference Publications
gro.rights.copyright© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
gro.date.issued2008
gro.hasfulltextFull Text
gro.griffith.authorMohd-Yasin, Faisal


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    Contains papers delivered by Griffith authors at national and international conferences.

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