EMC Modelling and Optimization for Reducing Capacitances of Interconnections with Arbitrary Shape in Multilayer VLSI Circuits

Abstract

This paper presents an EMC modelling method for the purpose of calculating the interconnect capacitance between VLSI interconnects based on the finite element method (FEM). Two- and three-dimensional interconnect models are simulated and the results of capacitance extraction are compared with experimental measurements, which proved the consistency and accuracy of FEM. Furthermore, optimizations of coupling capacitance are applied on two- and three-dimensional multilayer interconnection structures by the non-dominated sorting genetic algorithm II (NSGA-II), which shows a capacity for optimization. They are applicable to arbitrary structures in very-large-scale-integration (VLSI).