EMC Modelling and Optimization for Reducing Capacitances of Interconnections with Arbitrary Shape in Multilayer VLSI Circuits

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Title EMC Modelling and Optimization for Reducing Capacitances of Interconnections with Arbitrary Shape in Multilayer VLSI Circuits
Author Zhu, Boyuan; Lu, Junwei; Zhu, M.
Publication Title Proceedings of COMPUMAG2011
Editor Norio Takahashi
Year Published 2011
Publisher ICS
Peer Reviewed Yes
Published Yes
Publisher URI http://www.compumag2011.com/
Copyright Statement Copyright 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Research Centre Centre for Wireless Monitoring and Applications; Queensland Micro and Nanotechnology Centre
Faculty Faculty of Science, Environment, Engineering and Technology
Publication Type Conference Publications (Full Written Paper - Refereed)

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