Encryption in TECB Mode: Modeling, Simulation and Synthesis

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Title Encryption in TECB Mode: Modeling, Simulation and Synthesis
Author Reaz, M. B. I.; Ibrahimy, M. I.; Mohd-Yasin, Faisal; Wei, C. S.; Kamada, M.
Book Title AsiaSim 2007
Editor Jin-Woo Park, Tang-Gon Kim & Yun-Bae Kim
Year Published 2007
Place of publication Germany
Publisher Springer
Abstract The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59 MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software counterpart.
Peer Reviewed Yes
Published Yes
Alternative URI http://dx.doi.org/10.1007/978-3-540-77600-0_23
Chapter Number 25
Page from 205
Page to 215
ISBN 978-3-540-77599-7
Date Accessioned 2011-07-18; 2012-09-04T23:27:50Z
Research Centre Queensland Micro and Nanotechnology Centre
Faculty Faculty of Science, Environment, Engineering and Technology
Subject Inorganic Chemistry
URI http://hdl.handle.net/10072/46714
Publication Type Book Chapters
Publication Type Code b1x

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